1. Field of Invention
The present invention relates to a method for detecting the data strobe signal (DQS) of a double data rate (DDR) synchronous dynamic random access memory (SDRAM). More particularly, the present invention relates to a method for detecting the data strobe signal when a DDR SDRAM is outputting the data.
2. Description of Related Art
In present data process systems, a SDRAM module is often used in memory unit. The SDRAM module is synchronous with the system, the data is accessed at rising edges of the system clock. Therefore, an SDRAM module can provide a higher data transmission rate than a memory module having an independent clock.
A new memory module, called a double data rate (DDR) SDRAM module is similar to conventional SDRAM modules, but the data is accessed at both rising edges and falling edges of the system clock. Therefore, the DDR SDRAM module can provide double data transmission rate batter than the conventional SDRAM module. However, some problems have appeared because of the endless promotion of the system clock rate.
FIG. 1 shows a timing diagram of data reading from a DDR SDRAM. CLK is the system clock. When a signal RC is enabled at low logic state with one clock cycle long as a reading command and then after passing through the latency 102, the data will be transmitted in the data lines DQ at the rate of two data per clock cycle for reading. Assuming that eight data (data D0-D7) can be read in a read operation. When the data is transmitted in the data lines DQ, a data strobe signal DQS, which is synchronous with the data lines DQ, is provided. Each rising edge and falling edge of the signal DQS indicates the one data arriving in the data line DQ. Signal DQS also provides a low logic state preamble 104 with one clock cycle to indicate data is arriving before transmitting the first data D0 in the data lines DQ; and a low logic state postamble 106 with a half clock cycle to indicate the end of the data in the data lines DQ. Other than the foregoing conditions, the signal DQS maintains in a high impedance (HI-Z) status (between the high logic state and the low logic state), the signal DQS is a tristate logic signal.
After the data and the data strobe signal DQS are outputted from the DDR SRAM, data in the data lines DQ is received next.
On the whole, when a read command signal RC is asserted, an input enable signal TNI is enabled by a receiving unit to receive the data lines DQ and the data strobe signal DQS after a few time. When a preamble 104 of the data strobe signal DQS is detected by the input enable signal TNI, a high logic state of the input enable signal TNI will be maintained until a postamble 106 of the data strobe signal DQS is detected. The data receiving unit can provide a data reading signal ZI, which is synchronous with the data strobe signal DQS, for controlling the data receiving operation during the enable time of the input enable signal TNI, wherein the data receiving unit will read the data in the data lines DQ at both rising edges and falling edges of the data reading signal ZI.
For a variety of reasons, such as the acceleration of clock frequency and different layouts of memory modules and circuit boards among all kinds of products, therefore the latency 102 is not the same (not a constant) for various products As a result, the appearance time of the preamble 104 of the data strobe signal DQS is also variable.
In the conventional method, when asserting a reading command signal RC, the input enable signal TNI detects the preamble of the data strobe signal DQS after a fixed time. If the latency 102 is larger than the fixed time, the input enable signal TNI will detect a high impedance part of the data strobe signal DQS, and then the data reading signal ZI will be unknown state. If the latency 102 is smaller than the fixed time, the input enable signal TNI will detect the data strobe signal DQS after the preamble, this will cause data reading lost.